The present invention relates to a semiconductor device in which a power vertical DMOS (VDMOS) transistor and associated components are formed in a single semiconductor chip, and which is suitable for relatively low voltage and high current application and easy to fabricate.
Recently, there are proposed an integrated circuit semiconductor device (so-called power IC) in which a power VDMOS used as a switching element for various loads mounted on a vehicle, and other circuit elements constituting its drive circuit are monolithically formed in a single chip.
First, reference is made to a conventional example of a VDMOS device shown in FIG. 9. A VDMOS 41 shown in FIG. 9 is a n-channel type. An Si substrate 1 of this device is a so-called epitaxial substrate consisting of an n.sup.30 underlying layer 2 and an n epitaxial surface layer 3. The device further comprises a p channel region 4, an n.sup.+ source 5, a gate insulating oxide layer 6, a polycrystalline silicon gate electrode 7, a p.sup.+ channel contact region 8, a source electrode 9, an intermediate insulating layer 11, and a drain electrode 12. A final protective film (not shown) of PSG or the like is formed on the source electrode 9. The p.sup.+ channel contact region 8 is not always indispensable, but it is helpful for reliably making the potential of the p channel region 4 equal to the potential of the n.sup.+ source region 5.
In this VDMOS, a channel is formed in an upper portion 4a of the channel region 4 immediately below the gate electrode 7, and the n-type epitaxial surface layer 3 practically serves as a drain region of the VDMOS 41. The conductivity of the channel formed in the portion 4a is controlled by a voltage applied between the gate and source, and accordingly, the current flowing between the source and drain is controlled.
The VDMOS has the following advantages in addition to advantages of standard MOS transistors. The on resistance of the VDMOS is low, and it is easy to increase the withstand voltage and current capacity of the VDMOS. Furthermore, the VDMOS is uncostly because it can be fabricated without need for any special process. Therefore, the VDMOS transistors are becoming a mainstream of the power MOS transistors.
There are two different VDMOS circuits, an open drain connection shown in FIG. 10A, and a source follower connection shown in FIG. 10B.
In the open drain connection shown in FIG. 10A, a load 42 is connected between the drain terminal D of the VDMOS 41 and a supply voltage Vdd, and the source terminal S is connected to a ground. The gate terminal G of the VDMOS 41 receives an output voltage of a control circuit 43. In this configuration, the output voltage of the control circuit 43 which is applied to the gate terminal is always equal to a voltage between the gate and source of the VDMOS 41. Therefore, it is possible to control the current flowing through the load 42 by varying the output voltage of the control circuit 43 from the ground potential to the supply voltage Vdd. This configuration does not require a complicated circuit.
In the source follower connection shown in FIG. 10B, the load 42 is connected between the source terminal S of the VDMOS 41 and the ground (GND), and the drain terminal D is connected to the supply voltage Vdd. In this configuration, the potential of the source terminal S closely approaches to the supply voltage Vdd during the on period of the VDMOS, 41. Therefore, it is necessary to make the voltage of the gate terminal G higher than the supply voltage Vdd in order to ensure a sufficient gate-source voltage. For this reason, the source follower configuration requires a gate voltage booster circuit 44 between the control circuit 43 and the gate terminal G, for assisting the control circuit 43 which, in general, cannot increase the output voltage beyond the supply voltage Vdd.
For example, the gate voltage booster circuit 44 may take the form of a charge pump type booster circuit comprising an oscillator, condenser, and diode in combination.
The source follower configuration is disadvantageous in that it requires a complicated peripheral circuit, as explained above. However, this configuration is advantageous in that, when it is used for controlling a load mounted on a vehicle, the wiring can be simplified by using the vehicle body as a ground.
It is possible to integrate the VDMOS 41 and is peripheral circuit such as the control circuit 43 and the booster circuit 44 into a monolithic power IC. Such an integration makes it possible to reduce the size of the device, to reduce the packaging cost, to attain cost reduction and improvement of performance by omitting leads between components, and to develop new functions.
In the power IC, however, electrical isolation is problematical. Although isolation is not always required in the source follower configuration in which the potential of the substrate is fixed at the supply voltage, yet isolation between the VDMOS 41 and other integrated components is essential when the VDMOS 41 is used in the open drain configuration. In the open drain configuration, the potential of the substrate which is used as a drain region of the VDMOS 41 varies widely from the ground potential to the supply voltage Vdd.
The most common isolation technique is junction isolation using reverse-biased pn junctions. For example, it is possible to separate components from a VDMOS by forming them in a p-type well which is formed in the n-type surface layer 3 of FIG. 9 and which is connected to a ground to reverse-bias the pn junction between the p well and the n surface layer. Such a simple structure, however, is limited in application because it is not possible to form a complicated CMOS or a bipolar transistor in the p well.
A conventional integrated circuit device shown in FIG. 11 (R.S. Wrathall, "The Design of a High Power Solid State Automotive Switch in CMOS-VDMOS Technology", IEEE, Power Electronics Specialists Conference Record '85, P229-233) achieves isolation by using a three-layer substrate 45, an isolation diffusion wall 51 and an n-type buried layer 52. The npn three-layer substrate 45 is formed by forming a p-type intermediate layer 47 and an n-type top layer 48 on an n-type original substrate by two different epitaxial growths. The p isolation diffusion wall 51 reaching the p intermediate layer 47 is formed around a VDMOS 49.
The n buried layer 52 is formed under the n-type drain region of the VDMOS 49 so that the drain region is connected with the n bottom layer 46. In this way, an nMOS 53, a pMOS 54, a bipolar transistor 55 and other circuit elements are separated from the VDMOS 49 and the n bottom layer 46 by the p layer 47 and the p wall 51, so that electrical isolation can be achieved by connecting the p layer 47 and the p wall 51 to the ground. This conventional structure is applicable to both of the open drain configuration and the source follower configuration. This conventional structure can increase the flexibility in designing various transistors 53-55 formed in the n top layer 48 because the impurity concentration of the n top epitaxial layer 48 can be controlled independent of the concentration of the n bottom layer 46.
In the conventional device of FIG. 11, however, costly epitaxial growth is required twice, and moreover, the n buried layer 52 must be formed between the steps of epitaxial growth. Furthermore, a long heat treatment is required in order to diffuse the isolation diffusion wall 51 to the layer 47. Therefore, the conventional device of FIG. 11 is disadvantageous in that the fabrication process is complicated, time-consuming and costly.
Another conventional example is shown in FIG. 12. An integrated circuit device of FIG. 12 uses a lateral DMOS transistor (LDMOS) 56 in which an n.sup.+ drain contact region is formed in the surface of n-type drain region, and a drain electrode is formed on the top side rather than on the bottom side. It is easy to increase the withstand voltage of an LDMOS as in a VDMOS, but the on resistance of the LDMOS is two or more times as high as that of the VDMOS.
In the device of FIG. 12, isolation is relatively easy because the substrate is not used as a drain. This device separates the LDMOS 56 from nMOS 53, pMOS 54, bipolar transistors 55 and 59 and junction FET 60 by using a p-type substrate 57 and forming p-type isolation diffusion walls 51 in an n surface layer 58.
The structure of FIG. 12 is basically similar to that of a bipolar IC, so that the integration of the DMOS 56 and other circuit components is relatively easy, and the flexibility of IC design is high. However, the device of FIG. 12 is not suitable for high current application because the high on resistance of the LDMOS 56 incurs increase of the device's area and increase of the fabrication cost.
FIG. 13 shows a third conventional example of a power IC (as disclosed in ISSCC'86, Digest of Technical Papers, pages 22-23). The device of FIG. 13 is designed to employ the source follower configuration.
In the first and second conventional examples shown in FIGS. 11 and 12, isolation is required because they are designed to employ the open drain configuration. Unlike the first and second examples, the third example of FIG. 13 does not require isolation because its power MOS transistor is used only in the source follower configuration. However, the source follower configuration requires the gate voltage booster circuit 44 as shown in FIG. 10B. This requirement is not so disadvantageous if it is possible to integrate the booster circuit 44, the control circuit 43 and the VDMOS into a monolithic power IC. In the third example of FIG. 13, the VDMOS 41 and a CMOS 61 are formed in a single substrate. The CMOS 61 includes an nMOS formed in a p island formed in an n surface layer 3 of the substrate, and a pMOS formed directly in the n surface layer 3. The nMOS comprises an n.sup.+ ounce region 28, an n.sup.+ drain region 29, and a gate electrode 32. The pMOS comprises a p.sup.+ source region 35, a p.sup.+ drain region 36 and a gate electrode 37. The potential of the substrate 1 is fixed at the supply voltage because the VDMOS 41 is used in the source follower configuration. Therefore, the VDMOS 41 and the CMOS 61 can be operated independently.
However, such a simple structure of the third conventional example cannot reliably prevent interference between the VDMOS 41 and the CMOS 51 in a dynamic and transient state, so that this device is liable to cause malfunction as illustrated in FIGS. 14-16.
In an example shown in FIG. 14, power ICs are used for driving a DC motor M. When a power IC 62 and a MOS transistor 65 are on, and a power IC 63 and a MOS transistor 64 are off, then a current flows in direction shown by arrows I.sub.1 and I.sub.2 of FIG. 14, and the DC motor M is driven.
If the MOS transistor 65 is turned off at some instant, a so-called flywheel current continues flowing in a direction of I.sub.3 for a while after that instant. This current I.sub.3 flows into the source electrode of the VDMOS 41 of the power IC 63. In this case, if the device of FIG. 13 is used as the power ICs, holes 66 are injected from the source electrode 9 into the n surface layer 3 by the way of the p.sup.+ channel contact region 8 and the p channel region 4, as shown in FIG. 15, and the holes 66 tend to cause a latch-up of the CMOS 61 in the following manner.
A part of the injected holes 66 reach the p well 27 by diffusing in the n surface layer 3, and flow out through a p.sup.+ -type well contact region 67 and a grounded terminal. When the holes 66 flow through a base resistance 69 of a parasitic npn transistor 68 which is formed in the p well 27, the base potential of the parasitic npn transistor 68 is increased beyond the ground potential while on the other hand the potential of the n.sup.+ source region 28 is held at the ground potential. Therefore, the parasitic npn transistor 68 is turned on when an increase of this base potential becomes equal to or higher than a predetermined level (0.6 V). In the on state of the transistor 68, electrons are injected from the ground terminal GND into the n surface layer 3 by way of the n.sup.+ source region 28 and the p well 27. The injected electrons flow through the n surface layer 3 and an n.sup.+ substrate contact region 71, and flow out through the terminal connected to the supply voltage Vdd.
In this case, the electrons flow through a base resistance 73 of a parasitic pnp transistor 72 which is formed in the n surface layer 3. By so doing, the electrons decrease the base potential of the parasitic pnp transistor 72, so that the transistor 72 is also turned on.
The parasitic transistor 72 in the on state allows holes to flow from the power supply terminal into the p well 27 by way of the p.sup.+ source region 35 and the n surface layer 3. In this way, the CMOS 61 falls into a latch-up state in which the two parasitic transistors 68 and 72 provide positive feedback to each other so that the current is increased and a short circuit is formed between the power supply terminal and the ground terminal. The latch-up persists until the power supply is switched off.
Such a latch-up of the CMOS is serious especially in the power IC of FIG. 13. First, the VDMOS 41 of the power IC permits the current density several times higher than that of an output transistor (lateral MOSFET) of a standard CMOSIC. Therefore, the density of the current flowing into the p.sup.+ channel contact region 8 can become high, and the concentration of the holes injected into the n surface layer 3 can easily become high. For this reason, latch-up is more easily caused in the integrated CMOS of FIG. 13. Secondly, although the standard CMOSIC allows us to limit a surge current by inserting a resistance in series with the output and increasing an output impedance, yet such a measure is not possible in the power IC because the on resistance is increased too much.